1. Field of the Invention
This invention relates generally to processing time division multiple access communications system data and, more particularly, to a system for mapping a block of data between a communications slot time stamp and an addressable memory location.
2. Discussion of the Related Art
A common thread to cellular telephone communications, internet packet communications, modem communications, wireless LANS, etc. is the ever increasing need to process large amounts of communications data. Communications data comes in many forms, and the benefits associated with efficiently processing such data are abundantly clear. Time division multiple access (TDMA) provides a mechanism for sharing a transmission channel among multiple sources by allocating specific time slots to each source of data. This xe2x80x9ctransmission slot timingxe2x80x9d approach to handling communications data is quite common in the industry.
A unique problem arises, however, with respect to storage and retrieval of TDMA data. A particular concern is over removing processing bottlenecks at the storage and retrieval stages of data processing. For example, in a random access memory configuration, the word count or size of a data block must typically be known before an address location can be obtained. This requires knowledge of the content of the data block and substantially adds to processing time and resources. A random access approach also fails to appreciate the transmission slot timing nature of TDMA data. It is therefore desirable to provide a computerized method and system for storing and retrieving TDMA data that does not lead to processing bottlenecks associated with random access memory.
Approaches to sequential storage and retrieval of TDMA data have been suggested. Under such a system, a time stamp for a block of TDMA data contained in a communications slot would be converted into a memory address location without the need to know the content of the data. The data would be sequentially read into and out of a computer readable memory, such as a drum memory, and when the end of the memory is reached, the addressing mechanism would proceed to the beginning of the memory. Thus, by dividing the time stamp by a conversion factor representing the number of clock periods within a time slot, a sequential address location can be obtained for each time slot. For example, for a system in which the time counter is changed every 100 nanoseconds (or a 10 MHz clock rate) wherein the slot time is 13 micro-seconds, a TIME/130 calculation will be performed to determine an addressable memory location. The result is that for every 130 clock cycles, the time stamp for a communications slot will be converted into a sequential address in the drum memory. By so doing, TDMA data can be stored and retrieved in a manner which mimics the actual transmission slot timing of the data.
A difficulty exists, however, with implementing sequential storage and retrieval of TDMA data. Particularly, computerized division operations are costly and require many clock cycles to perform the necessary loops and processing decisions. Division also requires an unknown number of adding operations and shifting operations depending on the given time stamp. It is therefore desirable to provide a mechanism for mapping a block of TDMA data between a time stamp and a memory address which does not have the aforementioned division problems. Furthermore, since a counter is used to assign the time stamp to the data block, it is also desirable to account for counter roll-over in making the calculation.
In accordance with the teachings of the present invention, a memory access system for mapping a block of data between a time stamp and an addressable memory location is disclosed. In one embodiment, the system includes a slot time module, a calculation conversion module, and an addressing module. The slot time module determines the time stamp for the block of data. The calculation conversion module generates a preliminary memory location based on the time stamp and a conversion factor, where the conversion factor has a preliminary component. The addressing module removes the preliminary component from the preliminary memory location such that an addressable memory location is generated.
The calculation conversion module has a base conversion module for generating a partial address based on the time stamp and a base factor. A padding module generates a padded partial address based on the partial address and a predetermined number of coding bits. The calculation conversion module further includes a left-shift module for generating a left-shifted partial address based on the partial address and the predetermined number of coding bits. A summation module adds the padded partial address to the left-shifted partial address such that a preliminary memory location is generated. Preferably, the calculation conversion module further includes a scaling module for right-shifting the time stamp by one bit.
Further in accordance with the present invention, a computerized method for determining an addressable memory location for a block of data is disclosed. The method includes the steps of determining a time stamp for the block of data, and generating a preliminary memory location based on the time stamp and a conversion factor. The conversion factor has a preliminary component, and the method includes the step of removing the preliminary component from the preliminary memory location such that the addressable memory location is generated.
Additional objects, features and advantages of the invention will become apparent from the following description and the appended claims when taken in connection with the accompanying drawings.